The present invention relates to manufacturing of semiconductor devices, and more particularly, to forming devices based on strained-silicon with improved electrical characteristics.
There is a continuing drive in the semiconductor industry to fabricate devices exhibiting increased performance and decreased power consumption. Planar transistors, such as metal oxide semiconductor field effect transistors (MOSFET) are particularly well suited for use in high-density integrated circuits. As the size of MOSFETs and other devices decrease, the dimensions of source/drain regions, channel regions, and gate electrodes also decrease.
Strained-silicon transistors are typically fabricated by depositing a layer of silicon germanium (SiGe) on a bulk silicon wafer. A thin layer of silicon is subsequently deposited on the SiGe layer. The distance between atoms in a SiGe crystal lattice is greater than the distance between atoms in an ordinary silicon crystal lattice. There is a natural tendency of atoms inside different types of crystals to align with one another where one crystal is formed on another crystal. As such, when a crystal lattice of silicon if formed on top of a layer of SiGe, the atoms in the silicon crystal lattice stretch or xe2x80x9cstrainxe2x80x9d to align with atoms in the SiGe lattice. A resulting advantage of such feature is that the strained silicon experiences less resistance to electron flow and produces gains of up to 80% in speed as compared to ordinary crystalline silicon. However, strained-silicon technology has its disadvantages. The dielectric constant for SiGe is higher than silicon and results in higher junction capacitance. Second, the band-gap in SiGe is smaller than silicon and the smaller band-gap results in higher junction leakage. Accordingly, a need exists for an improved method of fabricating semiconductor devices based on a strained silicon structure that exhibit high-speed with lower junction capacitance and reduced junction leakage.
The miniaturization of planar transistors with short channel lengths requires very shallow source/drain junctions to avoid lateral diffusion of implanted dopants into the channel which causes leakage currents and poor breakdown performance. Shallow source/drain junctions, on the order of 1,000 xc3x85 or less, are generally required for acceptable performance in short channel devices.
Silicon on insulator (SOI) technology allows the formation of high-speed, shallow-junction devices. In addition, SOI devices improve performance by reducing parasitic junction capacitance. Although, SOI technology improves the performance of shallow-junction devices, devices that require deeper junctions do not benefit from SOI. For example, devices which are temperature sensitive or which require a deep implant perform better when formed in the bulk substrate.
Shallow trench isolation (STI) provides another technique to shrink device size. The use of STI significantly shrinks the area needed to isolate transistors better than local oxidation of silicon (LOCOS). STI also provides superior latch-up immunity, smaller channel width encroachment, and better planarity. The use of STI techniques eliminates the bird""s-beak frequently encountered with LOCOS.
Semiconductor devices generally suffer from decreased threshold voltages (Vt) at the silicon active region/STI interface. This is known as the fringing field effect. In devices with strained silicon layers formed over SiGe layers, the decreased Vt at the STI interface becomes more pronounced. The Vt at the strained silicon layer/STI interface is about 100-200 mV lower than central portions of the strained silicon layer. The decreased V, at the edge of the strained silicon layer causes increased off-state leakage.
There exists a need for methodology enabling the fabrication of semiconductor devices that exhibit the combined performance improvements of SOI technology, STI technology, and strained silicon technology. There exists a particular need for methodology enabling the fabrication of semiconductor devices with reduced off-state leakage and increased threshold voltage at the STI edge.
The above needs are met by a method of manufacturing a semiconductor device, the method comprising providing a semiconductor substrate comprising a silicon germanium (SiGe) layer on the semiconductor substrate layer and a strained silicon layer formed on the SiGe layer. Trenches are formed that extend from an upper surface of the strained silicon layer into the SiGe layer is formed. The trenches are enlarged by forming laterally extending regions which undercut a portion of the strained silicon layer. The trenches are filled with an insulating material to form trench isolation regions and a transistor is subsequently formed. The transistor comprises source/drain regions that are substantially within the strained silicon layer and a portion of each source/drain region is located over one of the laterally extending regions. In certain embodiments, the transistor is formed before the trenches.
The above needs are also met by a semiconductor device comprising a semiconductor substrate comprising a silicon-containing substrate. A SiGe layer is formed on the silicon-containing substrate and a strained silicon layer is formed on the SiGe layer. Trench isolation regions extend through the strained silicon layer into the SiGe layer and a portion of the trench isolation region extends laterally in the SiGe layer under the strained silicon layer. A transistor comprising source/drain regions which are located substantially within the strained silicon layer is formed and a portion of each source/drain region is located over the laterally extending portion of the trench isolation regions.
The above needs are further met by certain embodiments of the instant invention that provide a semiconductor device comprising a silicon-containing semiconductor substrate and a SiGe layer formed on the semiconductor substrate. A strained silicon layer is formed on the SiGe layer. A trench isolation region extends through the strained silicon layer into the SiGe layer, wherein a portion of the trench isolation region extends laterally into the SiGe layer undercutting the strained silicon layer.
The present invention addresses the needs for an improved high-speed semiconductor device with improved electrical characteristics and reduced off-state leakage.
The foregoing and other features, aspects, and advantages of the present invention will become apparent in the following detailed description of the present invention when taken in conjunction with the accompanying drawings.